1. Field of the Invention
The invention relates to a computer formed of many nodes in which each of the nodes includes a reconfigurable, many-function ALU pipeline connected to multiple, independent memory planes through a multi-function memory-ALU network switch (MASNET) and the multiple nodes are connected in a hypercube topology.
2. Description of Related Art
The computer of the present invention is both a parallel and a pipelined machine. The prior art does disclose in certain limited contexts the concept of parallelism and pipelining. See, for example, U.S. Pat. No. 4,589,067. However, the internal architecture of the present invention is unique in that it allows for most, if not all of the computer building blocks being simultaneously active. U.S. Pat. No. 4,589,067 is typical of the prior art in that it describes a vector processor based upon a dynamically reconfigurable ALU pipeline. This processor is similar to a single functional unit of the present invention's reconfigurable pipeline. In one sense the pipeline of the present invention's node is thus a pipeline of pipelines. Other structures that possibly merit comparison with the present invention are the Systolic Array by Kung, The MIT Data-Flow Concept and the concept of other parallel architectures.
The Systolic Array concept by H. T. Kung of Carnegie Melon University involves data which is "pumped" (i.e. flows) through the computer as "waves". Unlike the present invention, the Systolic Array system is comprised of homogenous building blocks where each building block performs a given operation. In the Systolic Array computer, as data flows through, the interconnection between identical building blocks remains fixed during a computation. At best, the configuration cannot be changed until all data is processed by the Systolic Array. In the present invention, by contrast, the interconnection between building blocks can be changed at any time, even when data is passing through the pipeline (i.e. dynamic reconfiguration of interconnects). The present invention is also distinct from the Systolic Array concept in that each building block (i.e. functional unit) of the node pipeline of the present invention can perform a different operation from its neighbors (e.g. functional unit 1 - floating point multiply; functional unit 2-integer minus; functional unit 3 - logical compare, etc.). In addition, during the course of computation, each building block of the present invention can assume different functionalities (i.e. reconfiguration of functionality).
The MIT Data-Flow computer is comprised of a network of hardware-invoked instructions that may be connected in a pipeline arrangement. The instruction processing is asynchronous to the "data-flow". Each data word is appended with a field of token bits which determines the routing of the data to the appropriate data instruction units. Each instruction unit has a data queue for each operand input. The instruction does not "fire" (i.e. execute) until all operands are present. The present invention include the concept of data flowing through a pipeline network of hardware functional units that perform operations on data (e.g. act as instructions that process data). However, by contrast, the present invention does not function in an asynchronous mode. Instead, data is fetched from memory and is routed by a switch (MASNET) to pipelined instruction units through the centralized control of a very high speed microsequencing unit. This synchronous control sequence is in sharp contrast to the asynchronous distributed data routing invoked by the Data Flow architecture.
Moreover, the present invention, unlike the Data-Flow Machine, has no token field (i.e. a data field that guides the data to the approriate functional unit) nor do the functional units have queues (i.e. buffers that hold operands, instructions, or results). The Data-Flow Machine has functional units waiting for data. The present invention has functional units that are continuously active. The control of the pipeline of the present invention is achieved by a central controller, referred to as a microsequencer, whereas the Data-Flow Machine uses distributed control. The present invention also has the ability to reconfigure itself based upon internal flow of data using the TAG field, a feature not found in Data-Flow machine. Furthermore, the Data-Flow computer does not effectively perform series of like or dissimilar computations on continuous streams of vector data (i.e. a single functional operation on all data flowing through the pipeline). In contrast the present invention performs this operation quite naturally.
There are two other principal differences between the parallel architecture of the present invention and other parallel architectures. First, each node of the present invention involves a unique memory/processor design (structure). Other parallel architectures involve existing stand-alone computer architectures augmented for interconnection with neighboring nodes. Second, other general multiple-processors/parallel computers use a central processing unit to oversee and control interprocessor communications so that local processing is suspended during global communications. The nodes of the present invention, by contrast, use an interprocessor router and cache memory which allows for communications without disturbing local processing of data.
The following U.S. Patents discuss programmable or reconfigurable pipeline processors: 3,787,673; 3,875,391; 3,990,732; 3,978,452; 4,161,036; 4,225,920; 4,228,497; 4,307,447; 4,454,489; 4,467,409; and 4,482,953. A useful discussion of the history of both programmable and non-programmable pipeline processors is found in columns 1 through 4 of U.S. Pat. No. 4,594,655. In addition, another relevant discussion of the early efforts to microprogram pipeline computers is found in the article entitled PROGRAMMING OF PIPELINED PROCESSORS by Peter M. Kogge from the March 1977 edition of COMPUTER ARCHITECTURE pages 63-69.
Lastly, the following U.S. Patents are cited for their general discussion of pipelined processors: 4,051,551; 4,101,960; 4,174,514; 4,244,019; 4,270,181; 4,363,094; 4,438,494; 4,442,498; 4,454,578; 4,491,020; 4,498,134 and 4,507,728.